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| The Cadence Encounter digital IC
design platform provides the fastest route to very large-scale, high-performance
chips. |
| The Encounter® platform covers a full spectrum nanometer-scale
digital integrated circuit (IC) design flow: synthesis, test, equivalence
checking, prototyping, signal integrity, routing, delay calculation, constraint
management, yield, power, and more. |
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| SoC Encounter L is a full-function, netlist-to-GDSII
configuration for flat designs of up to 5 million gates. This configuration has
a flexible licensing model. |
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| SoC Encounter XL is a full-function, RTL-to-GDSII
configuration for flat or hierarchical designs of more than 50 million gates. |
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| SoC Encounter GXL is a full-function, RTL-to-GDSII
configuration for advanced hierarchical designs of more than 100 million
gates. |
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| Encounter digital IC design
platform |
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